An epitaxial layer is the engine of compound semiconductor device where its composition, dopant concentration, homostructure or heterostructure, and thickness determine a device's electrical, thermal, mechanical, and/or optical characteristics. Because of special material properties, compound semiconductors are critical to the success of many technologies that have demonstrated widespread applications in defense, space, and commercial sectors. These applications and devices include but not limited to optoelectronics such as lasers, sensors, optical data storage, fiber optics, light emitting diodes (LED), and photovoltaics (PV), radio frequency (RF) and wireless systems, and microwave, millimeter-wave, radar, and satellite communication systems.
The prior art layer transfer methods separate grown epitaxy layer(s) or finished device structure from a parent wafer substrate to a daughter substrate. The prior art process typically is practiced as follows:                1) Deposit a backside contact and back surface reflector atop an inverted tandem structure which is grown on an etch stop layer over a first substrate. Mount the inverted tandem structure upside down on a second substrate. Remove the etch stop layer and thus the first substrate. Complete frontside processing of the tandem structure on the second substrate.        2) Deposit some layers on the first substrate, and other layers on the second substrate. Polish and bond the two-layered substrates by annealing. Detach the second substrate by a hydrogen implantation, leaving the desired layer combination on the first substrate.        3) Prepare a surface layer (surface conditioning) on a silicon substrate. Grow device layer on the surface treated layer. Attach a carrier to the device layer. Remove the surface layer and the silicon substrate.        4) Build a semiconductor device layer on a first substrate. Provide a set of first functional elements to connect in the semiconductor device layer. Attach a carrier substrate on top of the first functional elements. Remove the first substrate to expose the bottom side of the semiconductor device layer producing a first intermediate structure. Build a set of second functional elements on a foundation substrate to produce a second intermediate structure. Bond the first and the second intermediate structures to form a third intermediate structure. Remove the carrier substrate. Provide input output means on the exposed surface of the first functional elements to form the integrated device structure.        5) The epitaxial lift-off process allows the separation of a thin layer of compound semiconductor material from the substrate by strain-accelerated selective etching of an intermediate or sacrificial layer. Other means of removing the sacrificial layer in ELO include laser-assisted lift-off, ion bombardment.        6) Fabricate device on etch stop layer (epitaxial surface) grown on a substrate. Mesa etch to etch stop layer and pattern separate devices.        
Remove substrate using selective wet etching. Bond the device onto a host substrate using a transfer diaphragm.                7) Wax the top of the device. Lift-off in selective chemical etch of a sacrificial layer and removes the substrate. Attach the lift-off device to a glass substrate. Remove wax in chemical.        8) Implant the device template substrate. Activate and clean the surface of the device template substrate and the handle substrate. Initiate the bond at room temperature. Apply uniform pressure and heat to the stacked wafers to strengthen the bond and initiate exfoliation.        
These are just typical steps of course and are simplified here for instructive purposes. Some background references for this technology are identified below:                T. Kochiyaa, et al., “Anisotropy of lateral growth rate in liquid phase epitaxy of InP and its association with kink-step structures on the surface,” Applied Surface Science, 237, no. 1-4 (15 Oct. 2004): 235-241.        A. E. Nikolaev, et al., “SiC liquid-phase epitaxy on patterned substrates,” Journal of Crystal Growth,166, no. 1-4 (1 Sep. 1996): 607-611.        S. Sakai et al., “Selective Lateral Growth Mechanism of GaAs by Liquid-Phase Electroepitaxy,” Japanese Journal of Applied Physics, 33 (1994): 23-27.        K-W. Chung et al., “Lateral growth of GaAs over W by selective liquid phase epitaxy,” Applied Physics Letters, 52 (1988): 1716.        D. Dobosz et al., “Epitaxial lateral overgrowth of semiconductor structures by liquid phase epitaxy” International Journal of Materials and Product Technology, 22, no. 1/2/3 (2005): 50-63.        Z. R. Zytkiewicz et al., “Recent progress in lateral overgrowth of semiconductor structures from the liquid phase,” Crystal Research and Technology, 40, no. 4-5, (2005): 321-328.        D. Dobosz et al., “Liquid phase growth and characterization of laterally overgrown GaSb epitaxial layers,” Thin Solid Films, 412, (2002): 64.        Y. C. Liva et al., “Computational analysis of lateral overgrowth of GaAs by liquid-phase epitaxy,” Journal of Crystal Growth, 275, (2005): 953-957.        Z. R. Zytkiewicz, “Epitaxial Lateral Overgrowth of GaAs: Principle and Growth Mechanism,” Crystal Research and Technology, 34, 5-6, (1999): 573-582.        M. Wanlass et al., “Monolithic, Ultra-Thin GaInP/GaAs/GalnAsTandem Solar Cells,” NREL/PR-520-39852, Presented at the 2006 IEEE 4th World Conference on Photovoltaic Energy Conversion (WCPEC-4) held May 7-12, 2006 in Waikoloa, Hi.        M. S. Goorsky et al., “Engineered Layer Transfer Substrates for Heterogeneous Integration of III-V Compound Semiconductors,” 2008 The International Conference on Compound Semiconductor Manufacturing Technology.        R. Brendel, “Crystalline thin-film silicon solar cells from layer-transfer processes: a review,” Proc.10th Workshop on Crystalline Silicon Solar Cell Materials and Processes, Aug. 13-16, 2000, Copper Mountain, USA.        M. M. A. J. Voncken et al., “Etching AlAs with HF for Epitaxial Lift-Off Applications,” Journal of the Electrochemical Society, 151, no 5 (2004): G347-G352.        G. Roelkens et al., “Heterogeneous integration of III-V material and Silicon: fabrication and devices,” Proceedings Symposium IEEE/LEOS Benelux Chapter, (2004): 83-86.        
N. M. Jokerst et al., “The Heterogeneous Integration of Optical Interconnections Into Integrated Microsystems,” IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, 9, no. 2, MARCH/APRIL 2003.                X. Y. Lee et al., “Thin Film GaAs Solar Cells on Glass Substrates by Epitaxial Liftoff,” National renewable energy laboratory and sandia national laboratories photovoltaics program review meeting. AIP Conference Proceedings, 394, (1997): 719-727.        M. J. Archer et al., “Materials Processes for Ultrahigh Efficiency Lattice Mismatched Multijunction Solar Cells,” SPIE Optics+Photonics (2007): 6649-14.        P. Muller et al., “Surface melting of nanoscopic epitaxial films,” Surface Science, 529, no. 1-2, (2003): 59-94.        J. J. Daniele, “Peltier-induced LPE and composition stabilization of GaAlAs,” Applied Physics Letters, 27, no. 7, (1975): 373.        J. J. Daniele et al., “Electroepitaxial (peltier-induced) liquid phase epitaxy, compositional stabilization and x-ray analysis of thick (120 μm) In1-xGaxP EPILAYERS ON (100) GaAs,” Journal of Electronic Materials, 12, no. 6 (1983): 1015-1031.        U.S. Pat. No. 4,464,211 Logan et al.        U.S. Pat. No. 4,470,368 Reynolds, Jr. et al.        U.S. Pat. No. 4,768,463 Yoshida et al.        U.S. Pat. No. 4,186,045 Gatos et al.        U.S. Pat. No. 5,391,236 Dmitri et al.        
All of the above are incorporated by reference herein.
A number of fundamental barriers persist to mass production and commercialization of compound semiconductor devices namely: 1) material cost, 2) substrate size, and 3) component/sub-system integration. Despite the fact that the manufacturing cost of compound semiconductors has come down over time, it still remains much higher than silicon. Among the cost drivers, the cost of the crystalline substrate and epitaxial layer typically accounts for more than half of the finished wafer cost. Depending on the type of materials, crystal or substrate sizes also vary widely which raise challenges in tooling for wafer processing to make discrete devices or integrated circuits.
The other barrier is a lack of a technology platform (fabrication and integration platforms either monolithic or modular) versatile enough to intermix and integrate devices made from different materials for higher performance and/or functionality. Examples of needs for such an integration platform come from photonic integrated circuits in fiber optics, full spectrum utilization multijunction cells in photovoltaics, and transceiver in communication and radar systems.
Although epitaxy growth technologies have advanced with sophistications in equipment, epitaxy structure, and materials over the past decades, the manufacturing process of monolithically layering over crystalline substrate, wafer processing for device or integrated circuit (IC) formation, device/IC packaging, and board/module assembly has remained essentially the same.
Accordingly there is clearly a long-felt need for epitaxial systems and processes which are capable of addressing these deficiencies in the prior art.